Analysing randomised controlled trials with missing data : Choice of approach affects conclusions

Copyright © 2012 Elsevier Inc. All rights reserved. PMID: 22265924 [PubMed - indexed for MEDLINE]Peer reviewedPostprin

Using the literature to quantify the learning curve: a case study

Objective: To assess whether a literature review of a technology can allow a learning curve to be quantified. Methods: The literature for fibreoptic intubation was searched for studies reporting information relevant to the learning curve. The Cochrane Librar y, Medline, Embase and Science Citation index were searched. Studies that reported a procedure time were included. Data were abstracted on the three features of learning: initial level, rate of learning and asymptote level. Random effect meta-analysis was performed. Results: Only 21 studies gave explicit information concerning the previous experience of the operator(s). There were 32 different definitions of procedure time. From 4 studies of fibreoptic nasotracheal intubation, the mean starting level and time for the 10th procedure (95% confidence interval) was estimated to be 133s (113, 153) and 71s (62, 79) respectively. Conclusions: The review approach allowed learning to be quantified for our example technology. Poor and insufficient reporting constrained formal statistical estimation. Standardised reporting of non-drug techniques with adequate learning curve details is needed to inform trial design and costeffectiveness analysis

Toatie : functional hardware description with dependent types

Describing correct circuits remains a tall order, despite four decades of evolution in Hardware Description Languages (HDLs). Many enticing circuit architectures require recursive structures or complex compile-time computation — two patterns that prove difficult to capture in traditional HDLs. In a signal processing context, the Fast FIR Algorithm (FFA) structure for efficient parallel filtering proves to be naturally recursive, and most Multiple Constant Multiplication (MCM) blocks decompose multiplications into graphs of simple shifts and adds using demanding compile time computation. Generalised versions of both remain mostly in academic folklore. The implementations which do exist are often ad hoc circuit generators, written in software languages. These pose challenges for verification and are resistant to composition. Embedded functional HDLs, that represent circuits as data, allow for these descriptions at the cost of forcing the designer to work at the gate-level. A promising alternative is to use a stand-alone compiler, representing circuits as plain functions, exemplified by the CλaSH HDL. This, however, raises new challenges in capturing a circuit’s staging — which expressions in the single language should be reduced during compile-time elaboration, and which should remain in the circuit’s run-time? To better reflect the physical separation between circuit phases, this work proposes a new functional HDL (representing circuits as functions) with first-class staging constructs. Orthogonal to this, there are also long-standing challenges in the verification of parameterised circuit families. Industry surveys have consistently reported that only a slim minority of FPGA projects reach production without non-trivial bugs. While a healthy growth in the adoption of automatic formal methods is also reported, the majority of testing remains dynamic — presenting difficulties for testing entire circuit families at once. This research offers an alternative verification methodology via the combination of dependent types and automatic synthesis of user-defined data types. Given precise enough types for synthesisable data, this environment can be used to develop circuit families with full functional verification in a correct-by-construction fashion. This approach allows for verification of entire circuit families (not just one concrete member) and side-steps the state-space explosion of model checking methods. Beyond the existing work, this research offers synthesis of combinatorial circuits — not just a software model of their behaviour. This additional step requires careful consideration of staging, erasure & irrelevance, deriving bit representations of user-defined data types, and a new synthesis scheme. This thesis contributes steps towards HDLs with sufficient expressivity for awkward, combinatorial signal processing structures, allowing for a correct-by-construction approach, and a prototype compiler for netlist synthesis.Describing correct circuits remains a tall order, despite four decades of evolution in Hardware Description Languages (HDLs). Many enticing circuit architectures require recursive structures or complex compile-time computation — two patterns that prove difficult to capture in traditional HDLs. In a signal processing context, the Fast FIR Algorithm (FFA) structure for efficient parallel filtering proves to be naturally recursive, and most Multiple Constant Multiplication (MCM) blocks decompose multiplications into graphs of simple shifts and adds using demanding compile time computation. Generalised versions of both remain mostly in academic folklore. The implementations which do exist are often ad hoc circuit generators, written in software languages. These pose challenges for verification and are resistant to composition. Embedded functional HDLs, that represent circuits as data, allow for these descriptions at the cost of forcing the designer to work at the gate-level. A promising alternative is to use a stand-alone compiler, representing circuits as plain functions, exemplified by the CλaSH HDL. This, however, raises new challenges in capturing a circuit’s staging — which expressions in the single language should be reduced during compile-time elaboration, and which should remain in the circuit’s run-time? To better reflect the physical separation between circuit phases, this work proposes a new functional HDL (representing circuits as functions) with first-class staging constructs. Orthogonal to this, there are also long-standing challenges in the verification of parameterised circuit families. Industry surveys have consistently reported that only a slim minority of FPGA projects reach production without non-trivial bugs. While a healthy growth in the adoption of automatic formal methods is also reported, the majority of testing remains dynamic — presenting difficulties for testing entire circuit families at once. This research offers an alternative verification methodology via the combination of dependent types and automatic synthesis of user-defined data types. Given precise enough types for synthesisable data, this environment can be used to develop circuit families with full functional verification in a correct-by-construction fashion. This approach allows for verification of entire circuit families (not just one concrete member) and side-steps the state-space explosion of model checking methods. Beyond the existing work, this research offers synthesis of combinatorial circuits — not just a software model of their behaviour. This additional step requires careful consideration of staging, erasure & irrelevance, deriving bit representations of user-defined data types, and a new synthesis scheme. This thesis contributes steps towards HDLs with sufficient expressivity for awkward, combinatorial signal processing structures, allowing for a correct-by-construction approach, and a prototype compiler for netlist synthesis

The split-plot design was useful for evaluating complex, multi-level interventions but there is need for improvement in its design and report

Copyright © 2017 Elsevier Inc. All rights reserved.Peer reviewedPostprin

Determining information for inclusion in a decision-support intervention for clinical trial participation : A modified Delphi approach

Peer reviewedPostprin

Developing the Intervention and Outcome Components of a Proposed Randomised Controlled trial (RCT) of a National Screening Programme for Open Angle Glaucoma (OAG) : Medical Research Council funded trial platform study (G0701759): Study protocol

Postprin

Methodology and reporting characteristics of studies using interrupted time series design in healthcare

This research did not receive any specific grant from funding agencies in the public, commercial, or not-for-profit sectors for the design of the study and collection, analysis, and interpretation of data and in writing the manuscript. The Health Services Research Unit, University of Aberdeen, is core funded by the Chief Scientist Office of the Scottish Government Health and Social Care Directorates.Peer reviewedPublisher PD

Identification of outcomes reported for hospital antimicrobial stewardship interventions using a systematic review of reviews.

Funding: This work is a part of SY’s PhD, supported by the Elphinstone scholarship at the University of Aberdeen, Scotland.Peer reviewedPublisher PD

Relative effectiveness of robot-assisted and standard laparoscopic prostatectomy as alternatives to open radical prostatectomy for treatment of localised prostate cancer : a systematic review and mixed treatment comparison meta-analysis

© 2013 The Authors. BJU International © 2013 BJU International.Peer reviewedPublisher PD